Why AI Chips Made In The U.S. Are Being Sent To Taiwan — Creating A Major Bottleneck

[0:00] This is a chip made by Taiwan Semiconductor Manufacturing Company, [0:04] and we're here at its California offices for a rare interview about one of the next big [0:08] bottlenecks in the race to make enough chips to power AI, advanced packaging. [0:13] We build the silicon, we get the HBM from the memory vendors, [0:21] and then we build up the organic interposer in our packaging fab and do the pick and place. [0:26] But right now TSMC sends almost every chip like this, even the ones made in the US, [0:31] back to Taiwan for packaging. Because while you might think of microchips on the nanometer scale, [0:36] this is what a modern high-performance chip looks like. A bunch of smaller chips protected, [0:42] tested, bonded together in the packaging step of chip making. And it's almost all happening right [0:48] now in Asia. That's about to change. TSMC is breaking ground soon on two new advanced packaging [0:54] plants near its new chip fabs in Arizona. Packaging used to be an afterthought, right? Literally, [1:00] you would put your junior engineers on it. But now, obviously we know it's as important as the dye [1:08] itself. You simply can't ship a piece of silicon for a product without putting it in a package. [1:17] Now, NVIDIA has reserved the majority of TSMC's leading COOS packaging technology, [1:22] with TSMC reportedly outsourcing some packaging to third parties because capacity is so heavily booked. [1:28] It can emerge as a bottleneck very quickly if people are not making the capex investments [1:34] proactively to account for the surge in fab output that's going to be coming in the next couple of [1:39] years. Intel is the other major player with its EMIB packaging technology, primarily happening in [1:44] Vietnam and Malaysia. But the US-based chip maker is doing some advanced packaging in the US now, [1:50] in New Mexico and Arizona, where we got gowned up to see the clean room where it happens. [1:55] These are the chips or the dyes. The green rectangle there is what is called substrate or the package. [2:02] We went to TSMC and Intel to find out what exactly advanced packaging is, why it matters, [2:08] and what a constrained supply chain means for NVIDIA's competitors and the ability to fill insatiable demand [2:14] for AI chips. It's no secret that manufacturing the world's most advanced microchips is so expensive [2:31] and complex that only three global companies run fabs at the leading edge, TSMC, Intel, and Samsung. [2:37] Those same three are also the leaders in advanced packaging. Whether it's GPUs or CPUs from NVIDIA, [2:43] AMD or Intel, custom ASICs by Amazon or Google, every chip must be assembled onto a system so it can [2:50] interact with the world around it. This will connect to a circuit board and, you know, on a circuit board [2:57] you may have multiple of these parts. They become kind of a blade into a server rack. Paul Rousseau has [3:03] been at TSMC for 25 years and now heads up packaging solutions in North America. He likes to explain chip [3:09] packaging by comparing it to packaging for soda. If you think about Coca-Cola historically, the only way [3:15] you could buy a Coke was at a soda fountain. Once the bottling technology came along, [3:20] that revolutionized the distribution of Coca-Cola. And it evolved, right? We went from glass bottles to [3:27] aluminum cans to plastic bottles. But the primary function was still the same. It was to protect and [3:33] contain the product. And if you look back at our industry, it was exactly the same. Indeed, inside a [3:42] packaging lab, chips are coated with protective materials so they can be handled and installed. And they're [3:47] put through rigorous environmental testing. But most importantly is the packaging portion to [3:52] contain the chip and help it quickly and efficiently connect to a system. And as chips have gotten [3:58] exponentially more complex in the age of AI, standard packaging has evolved into advanced. [4:04] Most mobile chips and analog chips are not chiplets, but they used to come with one wafer. And that, [4:11] you know, comes out of the main chip factory. But now, multiple chips are being manufactured with [4:20] different technologies and sometimes even different places. And then they're pulled into one very large [4:28] chip. And you need advanced packaging to do that, to have the interconnects. And up until about five or [4:36] six years ago, nobody was doing this. We're putting multiple pieces of silicon together inside the package [4:43] and interconnecting them. It's really the natural extension of Moore's Law into the third dimension. [4:49] Here's how it works. First, individual chips, or dies, are bumped. Micron-scale metallic bumps [4:56] are added to the silicon surface as connection points for the electrical signals to travel through. [5:00] You can see the massive amounts of bumps. This is to connect to the outside world. [5:05] Then the dies are picked and placed, attached to the base layer of the package, the substrate, [5:10] that connects them to a larger system like a circuit board. The substrate is several layers of resin-type [5:15] material that routes signals and distributes power to the chip using copper. Companies like Intel are [5:21] also investing in glass substrates because it enables better control and finer features for the growing [5:26] systems needed for AI. Because as AI leaders like NVIDIA progress their chip density and performance [5:32] rapidly, their advanced packaging needs are evolving quickly too. They want to put more and more GPUs, [5:38] more and more high bandwidth memory into one package. And so we have shortages because this AI demand was [5:48] a little bit unexpected. So people had not put in enough capacity. While packaging is a necessary step, [6:01] the most advanced kind is what's in short supply. To understand why, let's break down the different [6:06] types. Many chips like CPUs are mounted directly to the base substrate in what's known as 2D or flip chip [6:13] packaging. But for more complex chips for AI, like GPUs, chip makers need 2.5D packaging, pioneered by TSMC [6:21] in 2012 with what it calls COOS, Chip on Wafer on Substrate, now used by customers like NVIDIA, Google, [6:28] Amazon and MediaTek. Chips are really side by side. So they're really 2D from that perspective. But we have [6:36] a communication channel underneath and that's the extra half dimension. That's what we call the interposer. [6:42] The interposer consists of additional layers with high density wiring that acts as a bridge between [6:47] multiple chips that sit on one substrate. This enables tight interconnections that are a game [6:52] changer for mounting stacks of high bandwidth memory directly around the chip. You might have heard of [6:57] the people refer to the memory wall, right? You just can't get enough memory inside your compute chip to [7:05] fully utilize it. So when we introduce COOS, we are able to bring the HBM memory right beside the compute in [7:13] a very efficient way. TSMC has moved through three different COOS generations, from COOS-S… [7:20] In the center it's like one big piece of silicon and there's four HBM around it. [7:24] …to COOS-R, now to COOS-L. You can see here two very large chunks of silicon in the middle [7:31] and then you have 12 HBM that surround it. COOS-L was first used in NVIDIA Blackwell GPUs that started [7:39] shipping out last year. And it's this COOS-L capacity that has everyone worried, because NVIDIA has [7:45] reportedly reserved the majority of it. We are seeing a lot of demand, and so we're trying to [7:50] respond to that demand. Obviously capacity has been tight. We're trying to solve that issue. [7:55] Do competitors to NVIDIA need to worry that so much COOS is reserved for NVIDIA? [8:03] I think we've always tried to be everyone's foundry, and we will keep trying to do that. [8:09] Of course, TSMC is not the only option. In 2017, Intel began its 2.5D packaging, [8:15] called EMIB – Embedded Multi-Die Interconnect Bridge. Instead of an interposer, EMIB adds a silicon [8:21] bridge within the substrate to allow the high bandwidth memory to communicate with the logic chip. [8:26] We're just embedding these really small pieces of silicon just where they're needed [8:30] to make an interconnect between them, to kind of connect them all up. So there's a cost advantage. [8:36] So instead of having a silicon interposer that covers basically all the chips that you're laying [8:42] down, it would basically connect just the edges of these chips, right? So it's going to save time, [8:49] it's going to save material, and it's going to allow you to work with smaller chipset sizes. [8:57] Samsung, which declined an interview for this story, calls its 2.5D packaging [9:02] iCube. And all the players are also working on what comes next after 2.5D – 3D, of course. [9:09] Samsung calls its 3D xCube. Intel's is Foveros Direct. TSMC's is SOIC – System on Integrated Chips. [9:17] That becomes true 3D technology. So instead of having the chips side by side, [9:22] now we put them one on top of the other. So the chips one on top of the other can really behave [9:28] as if they're one chip. Less space between chips means communication between them takes less power. [9:35] Our customers come and tell us that, you know, the amount of silicon they can put into a data center [9:41] is limited by the amount of power they have. And so if we can lower the power, then we can sell more [9:48] silicon and the data center becomes more powerful. TSMC says it'll be a couple years before we see [9:54] products made on SOIC. Memory companies like Samsung, SK Hynix and Micron already use 3D packaging [10:00] to stack dyes into high bandwidth memory inside advanced packaging fabs of their own. As they [10:06] hustle to get HBM out the door fast enough, memory companies and TSMC and Intel are also looking to [10:12] hybrid bonding to replace bumps with flat copper pads, boosting the number of chips that can fit in a stack. [10:19] Instead of a bump, we could do a pad to pad connection, which is almost no distance at all. [10:25] And so that gives us a better power performance. And it also gives us better electrical performance [10:33] since the shortest path is the best path. From 2D to 3D, right now the vast majority of advanced [10:47] packaging happens in Asia. And the challenge really becomes primarily for the U.S. is national security, [10:55] right? You have North Korea looking down at South Korea and all the challenges there. You have [11:02] Chinese boats and airplanes deciding to blockade Taiwan on occasion. [11:09] And at the volume leader, TSMC, 100% of packaging happens in Taiwan. Even ships made in TSMC's new [11:16] Arizona fab are sent to be packaged in Taiwan, where TSMC is ramping up two new packaging plants. [11:22] Historically, packaging migrated to Asia probably in the 1970s, right? And a lot of it had to do with [11:31] with cost and labor. Because at that time, packaging was very manually intensive. [11:36] Now, much of the process is handled robotically. And there's a big push to re-shore as many [11:42] manufacturing steps as possible amid ongoing geopolitical tensions and supply chain concerns. [11:47] So TSMC is about to build its first two U.S. packaging facilities, eventually adding high volume [11:53] packaging capacity near its chips being made in Arizona. Although it wouldn't share when construction [11:59] will begin. It's going to make it easier to get your turnaround time with the packaging rather than [12:06] have to ship it back to Asia and bring it back. Meanwhile, U.S.-based Intel does the majority of final [12:11] packaging assembly in China, Vietnam, and Malaysia. But it completes certain portions of EMIB and Foveros [12:18] entirely in the U.S., in New Mexico, Oregon, and at this site in Chandler, Arizona, near Intel's new 18A [12:24] fab that started volume production at the end of 2025. This is an Intel Xeon server chip and we are inside [12:31] Intel's advanced packaging lab where what happens is they take chips like 18A from fab 52 and they [12:38] actually connect them to the systems that we as consumers see like this with tens of thousands [12:44] of wires each thinner than a human hair. Although Intel has yet to solidify a major external customer [12:50] for its 18A fab, Gardner says Intel's had packaging customers since 2022 such as Amazon and Cisco. Now [12:58] Elon Musk has tapped Intel to package custom chips for SpaceX, XAI, and Tesla down the road. And NVIDIA is [13:04] looking to package at Intel too as part of its $5 billion investment in the chip maker last year. [13:10] I do think that the chip companies want to show the U.S. administration that they will do business [13:17] with Intel and the lower risk path with Intel is to do packaging. So could Intel find a major chip [13:24] manufacturing customer through the back door of advanced packaging? There's benefits of everything [13:29] being in one place and so yes with some customers that's kind of an inroad to that. It's one thing [13:34] to have the leading edge foundries with the tools and the engineers but that's only as as good as the [13:40] packaging in my opinion so you're not outsourcing that or relying upon a third party that you have [13:46] no control over for those capabilities. Smaller third-party packagers called OSATs handle part of the [13:54] process like Amcor, a TSMC and Intel partner that's building a packaging site in Arizona. Almost all chips end [14:01] up at an OSAT for the simpler steps and now more of the advanced steps too as TSMC struggles to keep [14:07] up with unprecedented demand. We're increasing our COAS capacity at 80% CAGR, our SOIC capacity 100% CAGR. [14:15] So our packaging numbers are growing very substantially. The world's largest OSAT, [14:21] ASE, sees advanced packaging sales doubling in 2026. It's building a huge new COAS site in Taiwan [14:28] where NVIDIA's Jensen Wang attended the opening of another new packaging site by ASE subsidiary Spill last [14:33] year. But as TSMC brings two advanced packaging plants to U.S. soil, this lesser-known step in the chip [14:40] making process may eventually help the U.S. regain some of its long-lost lead in silicon. [14:46] Are we talking a long time? Are we talking five years, ten years before we're going to see volume production for [14:51] advanced packaging from TSMC in the U.S.? We haven't given a specific timeline, [14:56] but we're trying to move as fast as we can to solve our customers' demands.